Peihuan Ni

Peihuan Ni 倪培洹

Currently, I am a master's student at the School of Artificial Intelligence, University of Chinese Academy of Sciences (UCAS), advised by Prof. Jian Cheng and Assistant Prof. Gang Li, at the Efficient Intelligent Computing and Learning Lab (CLab), Institute of Automation, Chinese Academy of Sciences, where I focus on efficient inference architectures.

Previously, I received my B.S. degree from the College of Electronic Science and Engineering at Jilin University (JLU).

Email / 简历 / CV / Scholar / Github / WeChat

Education

	University of Chinese Academy of Sciences School of Artificial Intelligence Institute of Automation, Chinese Academy of Sciences M.Eng. Candidate in Artificial Intelligence, 2024.9 – 2027.7 (Expected) Advised by Prof. Jian Cheng and Assistant Prof. Gang Li Beijing, China
	Jilin University College of Electronic Science and Engineering B.S. in Microelectronics Science and Engineering, 2020.9 – 2024.6 Jilin, China

Experience

Huawei
ICT BG
Research Intern, July. 2026 – July. 2027
Architecture Optimization on Ascend NPU

Research Interests

My research interests lie at the intersection of computer architecture and artificial intelligence. I am particularly interested in efficient AI systems, hardware-software co-design, hardware accelerators, and efficient inference for Large Language Models and Vision-Language-Action (VLA) models.

Publications

(First-author papers are highlighted)

Algo	ACE-VLA: Action Centric Evaluation for Token Pruning in Vision-Language-Action Models Peihuan Ni, Zeyu Zhu, Weifan Guan, Gang Li, Zitao Mo, Minnan Pei, Tielong Liu, Junwen Si, Qinghao Hu, Peisong Wang, Jian Cheng Conference on Robot Learning (CoRL), 2026.
Arch	APEX: Integer-only Non-linear Function Approximation for Efficient Cross-Modal Inference Peihuan Ni, Zitao Mo, Tielong Liu, Hongli Wen, Zeyu Zhu, Minnan Pei, Junwen Si, Weifan Guan, Peisong Wang, Qinghao Hu, Gang Li, Jian Cheng Design, Automation and Test in Europe Conference (DATE), IEEE, 2026.
Sys	KL-MoE: A Hierarchical MoE Pruning Framework Exploiting KL Divergence Zeyu Zhu, Gang Li, Minnan Pei, Zitao Mo, Peihuan Ni, Peisong Wang, Tielong Liu, Jian Cheng Design Automation Conference (DAC), ACM, 2026.
Arch	FLUTE: A LUT-Based Floating-Point Engine for Efficient LLM Acceleration Exploiting Core-Tail Hierarchical Alignment Tielong Liu, Zeyu Zhu, Gang Li, Zitao Mo, Chen BAI, Junwen Si, Peihuan Ni, Minnan Pei, Peisong Wang, Zhuoran Song, Xiaoyao Liang, Jian Cheng International Symposium on Microarchitecture (MICRO), IEEE/ACM, 2026.
Arch	DOMI: A Dataflow Optimization Framework for Efficient Mamba Inference on FPGAs Junwen Si, Gang Li, Tielong Liu, Peihuan Ni, Zeyu Zhu, Minnan Pei, Peisong Wang, Zhongfeng Wang, Jian Cheng IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Under-review.
Sys	DALI: A Workload-Aware Offloading Framework for Efficient MoE Inference on Local PCs Zeyu Zhu, Gang Li, Peisong Wang, Peihuan Ni, Tielong Liu, Minnan Pei, Junwen Si, Zhuoran Song, Xiaoyao Liang, Jian Cheng arXiV

Honors and Awards

Merit Student, University of Chinese Academy of Sciences (2025)
Third Prize, Chinese Mathematics Competitions (2023)
Second Prize, Contemporary Undergraduate Mathematical Contest in Modeling (2022)
Third Prize, Intel Cup National Undergraduate Electronic Design Contest (2022)

Service

Reviewer for WACV, EMNLP, CoRL.